In this type of semiconductor storage device, for example, a magnetoresistive element has heretofore been used as a storage element. As an example of the magnetoresistive element, an element referred to as a tunneling magnetoresistance element (hereinafter referred to as TMR) will be described. In this element, a tunneling insulation film is held between two magnetic layers, and information is stored by resistance of the tunneling insulation film, which changes with a state of magnetization of the magnetic layers.
FIG. 15 shows an example of the TMR reported in 2000 IEEE International Solid-State Circuits Conference DIGEST OF TECHNICAL PAPERS (pp. 128 and 129). As shown in FIG. 15, an antiferromagnetic layer (thickness of 10 nm) 101 formed of FeMn, a pinned layer (thickness of 2.4 nm) 102 formed of CoFe, a tunneling insulating layer 103 formed of Al2O3, and a free layer (thickness of 5 nm) 104 formed of an NiFe are stacked, and the TMR is formed. The antiferromagnetic layer 101 and the free layer 104 are connected to conductor wirings (not shown), respectively, in order to apply a voltage to the TMR. The magnetization of the pinned layer 102 is fixed in a certain direction by the antiferromagnetic layer 101. The free layer 104 is formed in such a manner that the layer is easily magnetized in a certain direction, and the magnetization direction can be changed by application of a magnetic field from the outside. In a direction in a horizontal plane of a laminate film (direction along the film surface), an easily magnetized direction is referred to as an easy axis, and a direction vertical to this easy axis and difficult to magnetize is referred to as a difficult axis. When a voltage is applied between the free layer 104 and the pinned layer 102, a current flows through the tunneling insulating layer 103, but an ohmic value changes with a relation between the directions of the magnetizations of the free layer 104 and the pinned layer 102. That is, resistance is low in a case where the magnetization directions are the same, and the resistance increases in a case where the magnetization directions are opposite to each other.
Next, an example using the TMR as a storage element of a nonvolatile memory will be described with reference to FIG. 16. This example has been reported in the 2000 IEEE International Solid-State Circuits Conference DIGEST OF TECHNICAL PAPERS (pp. 130 and 131). In the example of FIG. 16, two systems of wirings nonparallel to each other (i.e. crossing each other) are disposed above/below TMRs 107 arranged in an array. An upper wiring (referred to as the wiring B (B1, B2, . . . )) 108 is connected to the free layer of the TMR 107, and an antiferromagnetic layer of the TMR 107 is connected to a drain of a transistor 110 formed in a lower layer via a third wiring 109. An insulating layer (not shown) is disposed between the third wiring 109 and a lower layer which is a lower wiring (referred to as the wiring D (D1, D2, D3, . . . ) 111. To store data, when currents are passed through two wirings B, D, a synthetic magnetic field is generated in the vicinity of a region where these wirings cross each other, and the magnetization of the free layer of the corresponding TMR 107 is set in accordance with the direction of the current. Accordingly, the ohmic value of the TMR 107 can be changed. To read the data, the transistor 110 connected to the TMR 107 to read is brought into an on-state by a read word line (referred to as the wiring W (W1, W2, W3, . . . ) 112, the voltage is applied to the TMR 107 from the wiring B, and the ohmic value of the TMR is evaluated by the flowing current.
As methods in which the TMR is separated into elements to connect the upper wiring to an upper electrode for each TMR, there are lifting-off, heading by chemical mechanical polishing (CMP), a method using a via-hole and the like. In the lifting-off method, after forming a TMR material into a film, a lifting-off material is formed into a film, the TMR material film and lifting-off material film are processed into desired shapes, a TMR is formed and separated into elements, thereafter an insulation film is formed on the whole surface, thereafter the lifting-off material film is etched to remove the insulation film on the lifting-off material film, and an opening is formed above the TMR. Thereafter, an upper wiring material is formed into a film, and processed. In the heading by the CMP, instead of the lifting-off material, an upper electrode material is used, and similarly processed into a desired shape, the TMR and upper electrode are formed, and separated into elements, thereafter the insulation film is formed on the whole surface, and the surface is polished by the CMP to expose the upper electrode. Thereafter, the upper electrode material is formed into a film, and processed. In the method by the via hole, after a TMR having a desired shape is formed and separated into elements, an insulation film is formed on the whole surface, a resist mask which opens above the TMR is formed, and the insulation film is partially etched/removed to form an opening above the TMR. As another element separating method, there is a method in which an upper magnetic body is oxidized, and a TMR is processed into a desired shape. This will be described hereinafter.
FIGS. 17 to 20 are sectional views showing a method of producing a semiconductor storage device described in JP(A)-2000-353791 in order of steps, and FIG. 21 is a sectional view along line Z-Z′ of FIG. 20. This semiconductor storage device has a circuit including an NMOS switching transistor 121 formed on the surface of a P-type silicon substrate 120, and is prepared by a CMOS process which has heretofore been known. First, an N+ region 122 is formed in a surface portion of the P-type silicon substrate 120, and an insulating region 123 for element separation is formed. A polysilicon layer 124 forming a gate region is deposited, and a metal layer 125 is formed on the N+ region 122 and the polysilicon layer 124. A conductive layer 126 and a plug conductor 128 are formed on the metal layer 125, and thereafter a dielectric material 127 is charged. A lower-layer wiring is constituted of a conductive metal layer 132 and a digit wire 133 surrounded with a high-permeability layer 131, buried in an etching stop layer 129 and a silicon dioxide layer 130, and flattened. A dielectric layer 134 is deposited in such a manner as to cover the digit wire 133 and the silicon dioxide layer 130, and a conductive layer 135 is deposited in such a manner as to cover the dielectric layer 134 and the conductive metal layer 132. The dielectric layer 134 is disposed between the digit wire 133 and the conductive layer 135 to electrically separate the wire from the layer. The dielectric layer 134 is partially etched in order to form a window 136 for use in electrically connecting the plug conductor 128 to the conductive layer 135 via the conductive metal layer 132 in the conductive metal layer 132. After forming the window 136, the conductive layer 135 is deposited in such a manner as to cover the dielectric layer 134 and the conductive metal layer 132 by a thickness of about 50 nm. The surface of the conductive layer 135 is flattened by the CMP or the like in order to form a magnetic memory element on the conductive layer 135 (FIG. 17).
Next, a plurality of magnetic memory element blanket layers or magnetic memory blanket layers for forming a magnetic memory element are deposited on the surface of the conductive layer 135 by one of a physical deposition process, a chemical deposition process, or an ion beam deposition process. Magnetic materials such as alloys of Ni, Fe and/or Co are used in a bottom magnetic layer 140 and an upper magnetic layer 142 constituting the magnetic memory element. On the other hand, materials such as Al2O3 and Cu are used in a nonmagnetic layer 141 disposed between the bottom magnetic layer 140 and the upper magnetic layer 142. The bottom magnetic layer 140 functions, for example, as a hard magnetic layer, the direction of the magnetization thereof is fixed, and the direction of the magnetization of the upper magnetic layer 142 is free. The nonmagnetic layer 141 is formed by the following method. An aluminum film is deposited to cover the bottom magnetic layer 140, and thereafter the aluminum film is oxidized by an oxidation source by an RF producing oxygen plasma. In another method, aluminum is deposited together with oxygen on the nonmagnetic layer 140, and thereafter an oxidation process is executed in a heated or non-heated oxygen atmosphere. The layers in the magnetic memory element are very thin, for example, the thickness of the magnetic layer is 0.3 to 20 nm, and the thickness of the nonmagnetic layer is 0.3 to 10 nm. Next, a masking layer 143 is deposited to cover the upper magnetic layer 142 (FIG. 18).
A mask pattern obtained by patterning this masking layer 143 is formed on the upper magnetic layer 142, and the dielectric layer 134 is etched using this pattern as a mask. The conductive layer 135 electrically connects the magnetic memory element to the transistor 121 via the plug conductor 128. The conductive layer 135 is separated from the digit wire 133 by the dielectric layer 134. Next, a new mask pattern is formed on the masking layer 143. Moreover, this is used as a mask, the masking layer 143 and the blanket layers 140 to 142 are etched using a reactive ion etching process, a plurality of magnetic memory elements 144 are electrically defined, and further a plurality of contact metal pads (or conductive wires) 145 are formed. Following the formation of the plurality of contact metal pads 145, a part of the upper magnetic layer 142 is changed into a material having dielectric characteristics using one of an oxidation process and a nitriding process. In further detail, a selected region of the upper magnetic layer 142 is changed into an insulating material to form an inactive portion 142b. In a process of changing the upper magnetic layer 142 into a dielectric insulator, the contact metal pads 145 function as masks. As a result, after oxidation or nitriding, a plurality of active regions 142a are defined, and a new insulating portion (inactive portion 142b) is disposed (FIG. 19). The oxidation or nitriding process is used to change exposed portions of the blanket layers 140 to 142, accordingly these portions are changed to insulating materials, and the portions are set to be inactive.
After completing the oxidation or the nitriding of the upper magnetic layer 142 for forming the magnetic memory elements or the cells 144 as shown, a dielectric layer 146 is deposited in such a manner as to cover the magnetic memory elements 144 and the inactive portion 142b of the upper magnetic layer 142. Next, an etching stop layer 147 is deposited on the dielectric layer 146, and further a silicon dioxide layer 148 is deposited on the etching stop layer 147. Next, a mask (not shown) is patterned and formed on the silicon dioxide layer 148, and a trench for forming a bit line 149 is formed. The silicon dioxide layer 148 is etched to the etching stop layer 147 in accordance with the mask, and a trench for burying the bit line 149 is formed. Next, a Permalloy layer 150 is deposited on the silicon dioxide layer 148 and in the trench. The Permalloy layer 150 is etched by anisotropic etching, the Permalloy layer 150 is left on the side wall of the trench, and the Permalloy layer 150 is also left on the silicon dioxide layer 148 and a bottom part of the trench. After forming the Permalloy layer 150, an electrically conductive layer constituting the bit line 149 is deposited on the surface of a conductive line (contact metal pad 145) via the Permalloy layer 150. That is, a metal such as Al, W, or Cu is charged into the trench in order to form the bit line 149. Next, an unnecessary material on the silicon dioxide layer 148 is removed, and the surfaces of the silicon dioxide layer 148 and the bit line 149 are polished into flat surfaces. Finally, a Permalloy layer 151 is deposited and patterned on the silicon dioxide layer 148 and the bit line 149 (FIGS. 20, 21). The Permalloy layers 150, 151 envelop the bit line 149, accordingly a magnetic field produced by a bit current in the bit line 149 is concentrated on the magnetic memory elements 144, and other magnetic memory elements are shielded to protect information therein.
An operation method using two system wirings and transistors is similar to the above-described method.
However, with the above-described conventional memory structure, it has been difficult to enlarge a capacity, a large writing current has been required, and it has been difficult to reduce power consumption. Reasons for this will be described hereinafter.
A current is passed through a wiring to produce the magnetic field in order to change a magnetized state of the TMR. A magnitude of the magnetic field is inversely proportional to a distance from the wiring. Therefore, the wiring is brought as close to the TMR as possible. In the lifting-off method, they can be approached, but miniaturization is difficult in this technique, and it is difficult to enlarge the capacity. In the method of making the via-hole, since the distance is increased by the thickness of the insulation film on the TMR, it is difficult to reduce a writing current. In the method of heading the TMR by the CMP, the upper electrode needs to be left in a certain thickness so that the TMR itself is not polished in consideration of fluctuation of a polishing amount in a wafer plane. Therefore, the wiring is distant from the TMR by the thickness, and it is difficult to reduce the write current. In the method shown in FIGS. 17 to 21, the distance between the wiring and the TMR is increased by the thickness of the contact metal pad 145, and it is difficult to reduce the write current. Although the dielectric layer 146 and the etching stop layer 147 are formed after forming the contact metal pad 145, in FIG. 20, these layers are removed only on the contact metal pad 145. In actual, it is presumed that methods such as CMP and etching after deposition of the dielectric layer 146, and CMP after deposition of the etching stop layer 147 are used. However, when the methods are used, the contact metal pad 145 needs to be formed in a sufficient thickness.
Thus, there has been a problem that it is difficult to increase the capacity and decrease power consumption in the conventional techniques.